Gated field effect devices, such as transistors, are utilized in integrated circuitry, such as logic circuitry and memory circuitry. Exemplary memory includes static random access memory (SRAM), dynamic random access memory (DRAM) and floating gate programmable read-only memories (i.e., PROMs, EPROMs and EEPROMs). In a gated field effect device, a conductive gate is received proximate a channel region typically formed in lightly doped semiconductive material. Source/drain regions are received on opposing sides of the channel region. Upon application of a suitable threshold voltage to the gate, an electric field is created in the channel region, enabling or causing current to flow through the channel region from the source region to the drain region. Alternately by way of example only, field effect devices have also been utilized to establish fields beneath conductive gates for creating isolation between circuitry components within a semiconductive substrate.
Field effect devices include at least one conductive gate region and at least one gate dielectric region interposed between the conductive gate region and the semiconductive channel region. A common and predominantly used gate dielectric material has been SiO2. Yet, continued increase in circuit density and reduction in size of field effect device gate constructions have reached the point where the thickness of silicon dioxide gate dielectric layers has become so small that leakage currents, reliability and defects have become problematic. Accordingly, alternate materials have been utilized, for example insulative metal oxides.
Regardless, the substrates after gate fabrication are typically subjected to a reoxidation step which oxidizes a portion of the gate immediately adjacent the dielectric surface at the outer edges of the conductive gate material. Such effectively creates a so-called “smiling gate” structure in which tiny bird's beak structures are formed at the bottom corners of the gate stack. Such reoxidation can help to repair damage to dielectric and silicon surfaces resulting from the anisotropic etch typically utilized to form the gate stack and, as well, reduces hot electron degradation in the device in operation. An effect is to increase the thickness of the gate dielectric at the gate edges as opposed to the center of the gate. This has the apparent effect of lowering the electric field within the semiconductive material of the substrate at the source/drain edges, thereby reducing hot electron degradation.
While the invention was motivated in addressing the above identified issues, it is in no way so limited. The invention is only limited by the accompanying claims as literally worded, without interpretative or other limiting reference to the specification, and in accordance with the doctrine of equivalents.